FIG. 1 is a block diagram illustrating a typical microcontroller or microprocessor system. The system 10 has a central processing unit (CPU) 12 that communicates with a memory management interface 14 on a bidirectional bus. The memory management interface (MMI) 14 in turn communicates under direction of the CPU 12, with FLASH 16. RAM 17, and EEPROM 18 memories, on bidirectional buses.
FIG. 2 is a diagram illustrating a typical memory address map of physical memory and registers in the system illustrated in FIG. 1. The memory address map 20 is a programmer's view of the memories 16, 17, 18 shown in FIG. 1. It is controlled by the memory management interface 14. Along the left-hand axis of the memory address map is a series of hexadecimal byte addresses running from $0000 at the top through $FFFF at the bottom for a 64 kilobyte (KB) address range. In low memory are registers and RAM 22. This is followed by EEPROM 24. Starting at hex $4000 is a fixed map FLASH 28 followed by paged FLASH 30, 31, 32, 33, 34, 35, 36, 37 followed by another bank of fixed mapped FLASH 38 starting at hex $C000 and extending up to $FFFF. The second fixed map FLASH 38 contains interrupt and reset vectors. In FIG. 2, eight pages of paged FLASH 30, 31, 32, 33, 34, 35, 36, 37 are shown, each sharing the same address base ranging from $8000 through $BFFF.
FIG. 3 is a diagram illustrating a page mapping scheme for programmable memory utilized in the prior art. Four memories 50, 51, 52, 53 share the address space from $8000 through $BFFF. Each of the four memories 50, 51, 52, 53 has a corresponding set of address registers 40, 41, 42, 43 located at addresses $00F0 through $00FF. There is also a page select register (PPAGE) 44 utilized to select one of the pages of memory 50, 51, 52, 53: when the page select register 44 contains a value of $00, the first memory 50 is selected; when the page select register 44 contains a value of $01, the second memory 51 is selected; when the page select register 44 contains a value of $02, the third memory 52 is selected; and when the page select register 44 contains a value of $03, the fourth memory 53 is selected. The first set of registers 40 starting at address $00F0 is utilized to program the first memory 50. The second set of registers 41 starting a $00F4 is utilized to program the second memory 51. The third set of register 42 starting at $00F8 is utilized to program the third memory 52. Finally, the fourth set of registers 43, starting at $00FC is utilized to program the fourth memory 53.
FIGS. 4A and 4B together form a flow chart that illustrates programming four modules of FLASH memory in an architecture with a limited set of registers, utilizing the prior art architecture. The algorithm starts by setting the page select register (PPAGE) 44 to a value of $00, step 61. Register Y is then set to point at the start of FLASH memory in the window, step 62. An outer loop is then entered, starting with downloading a block to RAM, step 63. This is followed by setting an X register to the start of the RAM block, step 64. An inner loop is then entered which starts by programming word RAM to a first FLASH page (PPAGE=$00), step 65. The X and Y registers are then incremented, step 66, and a test is made whether the block is complete, step 67. As long as the block is not complete, step 67, the inner loop is repeated, starting with step 65. Otherwise, a test is made whether the window is done, step 68. As long as the window is not done, step 68, the outer loop is repeated, starting with step 63. Otherwise, when the window is done, step 68, programming for the first page of FLASH is complete. This is followed by identical code for pages $01 51, $02 52, and $03 53. Note that the page programming has been duplicated four times. This is primarily due to the fact that each of the four memory modules 50, 51, 52, 53 have a corresponding set of registers 40, 41, 42, 43. Therefore, the first set of memory programming registers 40 is used to program the first memory 50, and the second set of memory programming registers 41 is used to program the second memory 51, etc. It would be advantageous to reduce the overhead in programming, as illustrated in FIG. 4. Using a program register 40, 41, 42, 43 corresponding to each memory 50, 51, 52, 53 results in an inefficient programming module.